CEO (Founder):Shine Chung

Shine Chung graduated from Harvard University in the early 1980s. He started his career as an SRAM technologist and designer at AMD. He joined VLSI Design Associate as an ASIC circuit and logic designer in custom design projects later. Then he worked for HP Labs in the Super Workstation project since 1988. The RISC architecture he helped to define was transferred to Intel in 1994 as the Merced architecture and the corner stone of Itanium chips. After HP, he worked for Digital on StrongARM 1500, AMD on K5, and some startups on flash memory devices and designs. In 1999, he co-founded Audia Technologies, a hearing-aid IC and device company.
In 2003, he returned to Taiwan and worked for TSMC as a Director in Design Service Division to develop various IPs such as SRAM, embed-DRAM, electrical fuse, and emerging memories. He single-handedly built up the TSMC’s electrical fuse program from 0.13um to 90nm. He published two highly acclaimed papers on electrical fuse in VLSI Circuit Symposium 2007 and 2009, respectively. He was a two-time TSMC Corporate Innovation Award recipient in 2007 and 2008 for developing electrical fuse and logic bipolar device, respectively. He retired from TSMC in the early 2010 and founded Attopsemi Technology half a year later.
He was a member of technical program committee of ISSCC and VLSI Symposium from 2006 to 2010. He delivered tutorial, forum, and joined panel discussion in IEEE SOC Conference, VLSI Symposium, and ISSCC from time to time. He holds 61 U.S. patents, 20 pending, and 8 in preparations at the time of writing. He filed more than 30 patents in the U.S. and 9 in Taiwan/China after he founded Attopsemi Technology.


Sr. VP of Engineering:Wen-Kuan Fang

Wen-Kuan Fang received his MS degree from University of Michigan, Ann Arbor in the early 1990s. He joined Integrated Device Technology (IDT) as circuit designer in 1994. He was a design leader for various projects, such as asynchronous SRAM, synchronous SRAM, zero-bus-turn-around SRAM (ZBT) and content-addressable memory (CAM). In 2004, he returned to Taiwan and worked for TSMC as a manager of memory design team. He co-worked with RD and designed test vehicles from 65nm to 45nm. After successfully delivered two generations of test vehicles, he transferred to special design group as a department manager to lead both electrical fuse and SOI SRAM teams. He was responsible for design, delivery of production IPs and customer engagement.